Recently, the performance of a component such as a CPU constituting an information processing system (e.g., a server or a computer), especially, the bandwidth that can be processed by a signal of the component has been largely improved. Hence, a high speed performance of a transmission/reception circuit conducting data transmission/reception among a plurality of elements or circuit blocks between the chips such as the CPUs and inside a chip is required to improve the total bandwidth of the entire information processing system. Further, the high speed performance is also required for a transmission/reception circuit conducting data transmission/reception among boards or housings. In the transmission/reception circuit conducting the high speed data communication, a signal equalizing circuit (equalizer) is used to compensate for a data signal deterioration occurring in a communication channel.
An example of the equalizer is a speculative type decision feedback equalizer (DFE). The DFE assigns an offset voltage corresponding to a signal deterioration caused by an inter-symbol interference (ISI) occurring due to past data, to a data signal before being determined in a comparator, so as to compensate for the signal deterioration caused by the ISI. In the DFE, since a data signal is required to be compensated for each bit, a selection circuit (MUX) selecting a comparison result of the comparator is required to select a signal per time of a 1 bit width of data (1 unit interval (UI)). Accordingly, a delay time of a signal route for controlling the selection circuit is required to be shorter than the time of the 1 UI of data.
In the speculative type decision feedback equalization circuit, signals are assigned in advance with offset voltages corresponding to the possible kinds of data values, and a signal assigned with an offset voltage corresponding to the data that has been determined at the time of data determination is selected. Thus, the time required for the offset voltage assigning process may be reduced, as compared to assigning an offset voltage after the data decision.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 2009-231954, Peter Park, “A 4PAM/2PAM coaxial cable receiver analog front-end targeting 40 Gb/s in 90-nm CMOS,” a thesis submitted in conformity with the requirements for the degree of Master of Applied Science Graduate Department of Electrical and Computer Engineering in the University of Toronto, Jul. 30, 2008, and Optical Internetworking Forum (OIF), “Evolution of System Electrical Interfaces Towards 400G Transport,” [searched on Nov. 28, 2015], Internet <URL: http://www.oiforum.com/public/documents/30921b_Combined_Mkt_Focus_ECOC_Panel_OIF.pdf>.